The present invention relates to the field of semiconductor devices, their use, and manufacture. More particularly, in one embodiment the present invention provides an improved method and structure for reducing or improving substrate and interconnection capacitance in a semiconductor device.
Semiconductor devices are presently characterized by very small intrinsic delays as a consequence of a wide variety of improvements in their architecture, processing, and use. Self alignment techniques, improvements in lithography techniques, and improvements in dry etching techniques are exemplary of the changes which have resulted in devices having small intrinsic delays.
As semiconductor devices and their fabrication techniques have improved, the capacitance associated with interconnection lines plays an increasingly dominant role in the speed performance of an integrated circuit. An interconnect in an integrated circuit may include, for example, a metal or polysilicon layer deposited on a field oxide region. The field oxide region serves to create a high threshold voltage for a parasitic metal-insulator-silicon (MIS) device formed by the interconnection, the oxide, and the substrate. A heavily doped region below the oxide may be provided for better device isolation between, for example, adjacent bipolar transistors.
It is well known that device performance is impacted by the capacitance between the interconnect and the underlying substrate. Proposed solutions to the problems of interconnection capacitance include increasing the thickness of the field oxide used for isolation between devices, increasing substrate resistivity, and the like.
While meeting with some success, some prior solutions result in insufficient reductions in interconnect capacitance, particularly when applied to very small devices. Other solutions are uneconomical or create unacceptable complexities in the fabrication process. For example, significant increases in dielectric thickness may result in unacceptable encroachment, high defect density, or unacceptable topology in some devices. In spite of attempts to reduce interconnect capacitance, interconnect capacitance plays an increasingly significant role in device performance. Accordingly, an improved method o decreasing interconnect capacitance is needed.